ADM1029
http://onsemi.com
47
AIN REGISTERS
Table 53. REGISTER 05H GPIO PRESENT/AIN (POWER-ON DEFAULT 0????111)
Bit
Name
R/W
Description
0
GPIO 0 = 1
R/W
Indicates that GPIO0 is being used. Set to 1 on power-up, but can be
overwritten by software. Setting this bit to 0 means AIN0 is being used.
1
GPIO 1 = 1
R/W
Indicates that GPIO1 is being used. Set to 1 on power-up, but can be
overwritten by software. Setting this bit to 0 means AIN1 is being used.
2
GPIO 2 = 1
R/W
Indicates that GPIO2 is being used. Set to 1 on power-up, but can be
overwritten by software.
3
GPIO 3 = ?
R/W
Indicates that GPIO3 is being used. Setting this bit to 0 means TDM1
is being used. The ADM1029 can detect on power-up if TDM1 is
connected. If so, this bit is set to 0; otherwise it is set to 1. The default
setting can be overwritten by software.
4
GPIO 4 = ?
R/W
Indicates that GPIO4 is being used. Setting this bit to 0 means TDM1
is being used. The ADM1029 can detect on power-up if TDM1 is
connected. If so, this bit is set to 0; otherwise it is set to 1. The default
setting can be overwritten by software.
5
GPIO 5 = ?
R/W
Indicates that GPIO5 is being used. Setting this bit to 0 means TDM2
is being used. The ADM1029 can detect on power-up if TDM2 is
connected. If so, this bit is set to 0; otherwise it is set to 1. The default
setting can be overwritten by software.
6
GPIO 6 = ?
R/W
Indicates that GPIO6 is being used. Setting this bit to 0 means TDM2
is being used. The ADM1029 can detect on power-up if TDM2 is
connected. If so, this bit is set to 0; otherwise it is set to 1. The default
setting can be overwritten by software.
7
Reserved
R
Unused. Will read back 0.
NOTE: Question marks on this and following pages indicate bit settings that depend on the state of certain pins on power-up.
Table 54. REGISTER 50H, 51H AINX* BEHAVIOR (POWER-ON DEFAULT 00H)
Bit
Name
R/W
Description
0
Assert CFAULT
on HI_LIM = 0
R/W
When this bit is set, CFAULT
is asserted when AINx* exceeds the
AINx* high limit.
1
Alarm speed on HI_LIM = 0
R/W
When this bit is set, the fans go to alarm speed when AINx* exceeds
the AINx* high limit.
2
INT
on HI_LIM = 0
R/W
When this bit is set, INT
is asserted when AINx* exceeds the AINx*
high limit.
3
Alarm below low = 0
R/W
This bit indicates whether an alarm (INT
, CFAULT
or Alarm Speed) is
asserted when AINx* goes above or below the Low Limit. 1 = above.
0 = below.
4
Assert CFAULT
on LO_LIM = 0
R/W
When this bit is set, CFAULT
is asserted when AINx* crosses the
AINx* low limit. Bit 3 decides whether CFAULT
is asserted for going
above or below the Low Limit.
5
Alarm speed on LO_LIM = 0
R/W
When this bit is set, the fans go to alarm speed when AINx* crosses
the AINx* low limit. Bit 3 decides whether Alarm Speed is asserted for
going above or below the Low Limit.
6
INT
on LO_LIM = 0
R/W
When this bit is set, INT
is asserted when AINx* crosses the AINx*
low limit. Bit 3 decides whether INT
is asserted for going above or be-
low the Low Limit.
7
Latch AIN Fault = 0
R/W
This bit latches an out-of-limit event (i.e., when AINx* goes above the
high limit or crosses the low limit) on the AINx* channel. This bit is
cleared by writing a 0 to it.
* x denotes the number of the AIN channel. Register 50h controls AIN0 and 51h controls AIN1.
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